EEE241 DLDlect 03

EEE241
Digital Logic Design

CHAPTER NO. 3
DR. RIAZ HUSSAIN
ASSISTANT PROFESSOR
DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING
COMSATS UNIVERSITY ISLAMABAD
05/20/2023
Review 2
 Define the following:
 Closure, Associative law, Commutative law, Identity element, Inverse and Distributive
 What is the difference between ordinary algebra and Boolean algebra w.r.t.
distributive law
 What is a postulate?
 What is “Duality” and what is its utility?
 What is involution?
 What is operator precedence rule for Boolean algebra?
 How can you convert a Boolean expression in SoP canonical form to PoS canonical
form?
 What are the standard SoP and PoS forms?
 What is the truth table for XOR and XNOR gates
 What are the digital logic families?
 Define “fan out” and “propagation delay”?
Riaz Hussain (rhussain@comsats.edu.pk) CUI-IBD-ECE EEE241 DLD Chapter-03

05/20/2023
Outline 3
 Introduction to gate-level minimization
 The map method
 Four variable K-Map
 PoS simplification
 Don’t care condition
 NAND and NOR implementation
 Other two level implementations
 XOR function
 HDL

05/20/2023
Must Reading 4
 Chapter No. 3: Gate-Level Minimization

05/20/2023
Introduction 5
“Gate-level minimization is the design task of finding an

optimal gate-level implementation of the Boolean functions
describing a digital circuit”
 Manually difficult for several inputs

 Logic synthesis tools can do it very efficiently and quickly,
BUT
 Designer must understand underlying mathematical
description
“will enable you to execute a manual design of simple circuits,

preparing you for skilled use of modern design tools”
05/20/2023
The Map Method
 Truth table is unique, but algebraic expressions can be many 6
 Rules for simplification of an algebraic expressions are intuitive and not
straight forward
 Karnaugh map or K-map:
 simple, straightforward procedure for minimizing Boolean functions
 Diagram made of square
 Each square represents one (1) min term
 Enables visualize all possible ways of expressing a Boolean algebraic
function
 Can give simplest expression
 Simplest expression?
 Minimum number of terms and with the smallest possible number of
literals in each term
 expression produces a circuit diagram with a minimum number of
gates and the minimum number of inputs to each gate
05/20/2023
Karnaugh Map 7
 Adjacent Squares
 Number of squares = number of combinations
 Each square represents a minterm
 2 Variables  4 squares
 Each two adjacent squares differ in one variable
 Two adjacent minterms can be combined together
Note: adjacent squares horizontally and vertically NOT diagonally
Example:F = x y + x y’
= x ( y + y’ )
=x
05/20/2023
Two Variable K-Map 8
 Example
x y F Minterm
m0 m1
0 0 0 0 m0
1 0 1 0 m1 m2 m3
2 1 0 0 m2
3 1 1 1 m3
y
y x 0 1
0 0 0
x 0 1 1
05/20/2023
… continued 2
Two

Variable
Example
K-Map 9
x y F Minterm
m0 m1
0 0 0 0 m0
1 0 1 1 m1 m2 m3
2 1 0 1 m2
3 1 1 1 m3
y
y x 0 1
0 1 0
x 1 1 1
05/20/2023
Three-variable Map 10
x y z Minterm m0 m1 m3 m2
0 0 0 0 m0
m4 m5 m7 m6
1 0 0 1 m1
2 0 1 0 m2
yz
3 0 1 1 m3 x 00 01 11 10
4 1 0 0 m4
0
5 1 0 1 m5
6 1 1 0 m6 1
7 1 1 1 m7
05/20/2023
m0 m1 m3 m2
• Example
m4 m5 m7 m6
x y z F Minterm
yz
0 0 0 0 0 m0 x 00 01 11 10
1 0 0 1 0 m1 0
2 0 1 0 1 m2 1
3 0 1 1 1 m3
y
4 1 0 0 1 m4
5 1 0 1 1 m5 0 0 1 1
6 1 1 0 0 m6 x 1 1 0 0
7 1 1 1 0 m7 z

05/20/2023
m0 m1 m3 m2
• Example
m4 m5 m7 m6
x y z F Minterm
yz
0 0 0 0 0 m0 x 00 01 11 10
1 0 0 1 0 m1 0
2 0 1 0 0 m2 1
3 0 1 1 1 m3
y
4 1 0 0 1 m4
5 1 0 1 0 m5 0 0 1 0
6 1 1 0 1 m6 x 1 0 1 1
7 1 1 1 1 m7 z Extra

05/20/2023
Three-variable Map y
13
• Example
x y z F Minterm 0 1 1 0
0 0 0 0 0 m0 x 0 1 1 0
1 0 0 1 1 m1 z
2 0 1 0 0 m2
3 0 1 1 1 m3
4 1 0 0 0 m4
5 1 0 1 1 m5 y
6 1 1 0 0 m6 0 1 1 0
7 1 1 1 1 m7
x 0 1 1 0
Riaz Hussain (rhussain@comsats.edu.pk) CUI-IBD-ECE EEE241 DLD z
Chapter-03
05/20/2023
m0 m1 m3 m2
• Example
m4 m5 m7 m6
x y z F Minterm
yz
0 0 0 0 1 m0 x 00 01 11 10
1 0 0 1 0 m1 0
2 0 1 0 1 m2 1
3 0 1 1 0 m3
y
4 1 0 0 1 m4
5 1 0 1 1 m5 1 0 0 1
6 1 1 0 1 m6 x 1 1 0 1
7 1 1 1 0 m7 z

05/20/2023
Four-variable Map 15
m0 m1 m3 m2
w x y z Minterm
0 0 0 0 0 m0 m4 m5 m7 m6
1 0 0 0 1 m1 m12 m13 m15 m14
2 0 0 1 0 m2
3 0 0 1 1 m3 m8 m9 m11 m10
4 0 1 0 0 m4
m5
yz
5 0 1 0 1
6 0 1 1 0 m6 wx 00 01 11 10
7 0 1 1 1 m7 00
8 1 0 0 0 m8
9 1 0 0 1 m9
01
10 1 0 1 0 m10
11 1 0 1 1 m11
11
12 1 1 0 0 m12
13 1 1 0 1 m13
m14
10
14 1 1 1 0
15 1 1 1 1 m15
05/20/2023
Four-variable
yz Map 16
• Example wx 00 01 11 10
w x y z F Minterm 00
0 0 0 0 0 1 m0
1 0 0 0 1 1 m1 01
2 0 0 1 0 1 m2 11
3 0 0 1 1 0 m3
4 0 1 0 0 1 m4 10
5 0 1 0 1 1 m5
6 0 1 1 0 1 m6
y
7 0 1 1 1 0 m7
m8
1 1 0 1
8 1 0 0 0 1
9 1 0 0 1 1 m9 1 1 0 1
10 1 0 1 0 m10 x
0 1 1 0 1
11 1 0 1 1 0 m11 w
12 1 1 0 0 1 m12 1 1 0 0
13 1 1 0 1 1 m13 z
14 1 1 1 0 1 m14
15 1 1 1 1 0 m15
05/20/2023
•Example
Simplify: F = A’ B’ C’ + B’ C D’ + A’ B C D’ + A B’
C’
C
B
A
D

05/20/2023
•Example
Simplify: F = A’ B’C’ + B’ C D’ + A’ B C D’ + A B’ C’
C
1 1
B
A
D

05/20/2023
•Example
C’
C
1
B
A
1
D

05/20/2023
•Example
Simplify: F = A’ B’ C’ + B’ C D’ + A’ B C D’ + A B’ C’
C
1
B
A
D

05/20/2023
•Example
Simplify: F = A’ B’ C’ + B’ C D’ + A’ B C D’ + A B’ C’
C
B
A
1 1
D

05/20/2023
•Example
C’
C
1 1 1
1 B
A 1 1 1
D

05/20/2023
Five-variable Map 23
DE D DE D
BC 00 01 11 10 BC 00 01 11 10
00 m0 m1 m3 m2 00 m16 m17 m19 m18
01 m4 m5 m7 m6 01 m20 m21 m23 m22
C C
11 m12 m13 m15 m14 11 m28 m29 m31 m30
B B
10 m8 m9 m11 m10 10 m24 m25 m27 m26
E E
A=0 A=1

05/20/2023
Five-variable Map 24
A=0
A=1

05/20/2023
Implicants 25
Implicant:
C
Gives F = 1
1
1 1 1
B
1 1 1
A
1
D

05/20/2023
Prime Implicants 26
Prime Implicant:
Can’t grow beyond C
this size 1
1 1 1
B
1 1 1
A
1
D

05/20/2023
Essential Prime Implicants27
8 Implicants, 5 Prime implicants, 4 Essential prime implicants
Essential Prime Not essential
Implicant: C
No other choice 1
1 1 1
B
1 1 1
A
1
D
To ensure that a minimum solution is found, select essential prime
implicants first. Then find a minimum set of prime implicants that
cover the remaining 1's on the map.
05/20/2023
Product of Sums Simplification
28
y
w x y z F F
0 0 0 0 0 1 0 1 1 0 1
1 0 0 0 1 1 0
2 0 0 1 0 1 0 1 1 0 1
x
3 0 0 1 1 0 1 1 1 0 1
4 0 1 0 0 1 0 w
1 1 0 0
5 0 1 0 1 1 0
6 0 1 1 0 1 0 z
7 0 1 1 1 0 1 y
8 1 0 0 0 1 0
9 1 0 0 1 1 0 1 1 0 1
10 1 0 1 0 0 1 1 1 0 1
11 1 0 1 1 0 1 x
1 1 0 1
12 1 1 0 0 1 0 w
13 1 1 0 1 1 0 1 1 0 0
14 1 1 1 0 1 0 z
15 1 1 1 1 0 1

05/20/2023
Don’t-Care Condition 29
•Example
A B C $ Value You can only

0 0 0 $ 0.00
drop one coin at
0 0 1 $ 0.05
0 1 0 $ 0.10 a time.
0 1 1 Not possible
1 0 0 $ 0.25
1 0 1 Not possible Used as
1 1 0 Not possible “don’t care”
1 1 1 Not possible
05/20/2023
•Example A
Logic F
B
Circuit
A B C F
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 x
1 0 0 1 Don’t care
1 0 1 x what value F
1 1 0 x
1 1 1 x
may take
05/20/2023
•Example A
B F
0 1 x 0
A 1 x x x
C

05/20/2023
• Example F (w, x, y, z) = ∑(1, 3, 7, 11, 15)
d (w, x, y, z) = ∑(0, 2, 5)
x=0 x=1 x=0
y y
x 1 1 x x x
x=1 x 1 0 x 0
x x
1 0 0 0
w w
1 0 0 0
z z

05/20/2023
Tabulation Method
33
Input: f as a set of minterms
on
Output: f on as a set of
1. All Essential Prime Implicants
2. As Few Prime Implicants as Possible
Finding as few Prime Implicants as Possible

is an NP-Hard Problem!!!!!
• Reduces to the “Set Covering” Problem for Unate Functions
Unate function – a constant or is represented by a SOP using
either uncomplemented or complemented literals for each
variable
• Reduces to the “Minimum Cost Assignment” Problem for Binate
Functions (ex. EXOR)
This is 2-Level (SOP) Optimization (Minimization)

05/20/2023
Tabulation Method
• STEP 1:
34
– Convert Minterm List (specifying f on) to Prime Implicant List
• STEP 2:
– Choose All Essential Prime Implicants
– If all minterms are covered
HALT
Else
GO To STEP 3
• STEP 3:
– Formulate the Reduced Cover Table Omitting the rows/cols of EPI
– If Cover Table can be Reduced using Dominance Properties, Go To Step 2
– Else Must Solve the “Cyclic Cover” Problem
1) Use Exact Method (exponentially complex)
2) Use Heuristic Method (possibly non-optimal result)
NOTE: “Quine-McCluskey” Refers to Using a “Branch and Bound” Heuristic

NOTE: “Petrick’s Method” is Exact Technique – Generates all Solutions
Allowing the Best to be Used
05/20/2023
Tabulation Method – STEP 1
35
1. Partition Prime Implicants (or minterms) According to Number of 1’s
2. Check Adjacent Classes for Cube Merging Building a New List
3. If Entry in New List Covers Entry in Current List – Disregard Current

List Entry
4. If Current List = New List

HALT
Else
Current List  New List
New List  NULL
Go To Step 1

05/20/2023
STEP 1 - EXAMPLE
36
f on = {m0, m1, m2, m3, m5, m8, m10, m11, m13, m15} =  (0, 1, 2, 3, 5, 8, 10, 11, 13, 15)

05/20/2023
STEP 1 - EXAMPLE
37
f on = {m0, m1, m2, m3, m5, m8, m10, m11, m13, m15} =  (0, 1, 2, 3, 5, 8, 10, 11, 13, 15)

05/20/2023
STEP 1 - EXAMPLE
38
f on = {m0, m1, m2, m3, m5, m8, m10, m11, m13, m15} =  (0, 1, 2, 3, 5, 8, 10, 11, 13, 15)

05/20/2023
STEP 1 - EXAMPLE
39
f on = {m0, m1, m2, m3, m5, m8, m10, m11, m13, m15} =  (0, 1, 2, 3, 5, 8, 10, 11, 13, 15)
Question: Can this be

done on a CCM?
How modified?
f on = {A,B,C,D,E,F,G} = {00--, -01-, -0-0, 0-01, -101, 1-11, 11-1}

05/20/2023
STEP 2 – Construct Cover Table
40
• PIs Along Vertical Axis (in order of # of literals)
• Minterms Along Horizontal Axis
NOTE: Table 4.2 in book is incomplete

05/20/2023
STEP 2 – Finding the Minimum Cover
41
• Extract All Essential Prime Implicants, EPI
• EPIs are the PI for which a Single x Appears in a Column
• C is an EPI so: f on={C, ...}

• Row C and Columns 0, 2, 8, and 10 can be Eliminated
Giving Reduced Cover Table
• Examine Reduced Table for New EPIs
05/20/2023
STEP 2 – Reduced Table
42
Distinguished Column
Essential row
•The Row of an EPI is an

Essential row
•The Column of the Single x in
the Essential Row is a
Distinguished Column
05/20/2023
Row and Column Dominance
43
• If Row P has x’s Everywhere Row Q Does
Then Q Dominates P if P has fewer x’s
• If Column i has x’s Everywhere j Does

Then j Dominates i if i has fewer x’s
• If Row P is equal to Row Q and Row Q does not cost more than Row P,
eliminate Row P, or if Row P is dominated by Row Q and Row Q Does
not cost more than Row P, eliminate Row P
• If Column i is equal to Column j, eliminate Column i or if Column i

dominates Column j, eliminate Column i

05/20/2023
STEP 3 – The Reduced Cover Table
44
• Initially, Columns 0, 2, 8 and 10 Removed
• No EPIs are Present

• No Row Dominance Exists
• No Column Dominance Exists
• This is Cyclic Cover Table
• Must Solve Exactly OR Use a Heuristic
The Cyclic Cover Table
05/20/2023
45
• For now, we Arbitrarily Choose a PI
• Later we will Study Exact and Heuristic Methods
• Arbitrarily Choose F so: fon={C, F, ...}

This Choice May Lead to a Non-Optimal Result!!!!
• Form Reduced Cover and Go To Step 2

05/20/2023
STEP 3 – Dominance
46
• Initially, Reduced Table has Columns 11 and 15
Removed
• G is Dominated by E
• B is Dominated by A
• Form Reduced Cover Table and Go To Step 2

05/20/2023
STEP 2 – The Reduced Cover
47
• Initially, Table has Rows G and B Removed
• Secondary EPIs – A and E

• All Columns Covered
• Eliminate D
• fon={C, F, A, E}

05/20/2023
Result Check
48
cd cd
ab 00 01 11 10 ab 00 01 11 10
00 1 1 1 1 00 1 1 1 1
01 1 01 1
11 1 1 11 1 1
10 1 1 1 10 1 1 1
Initial Minterm List Final Result

fon = {m0, m1, m2, m3, m5, m8, m10, m11, m13, m15} f on={A, C, E, F}
=  (0, 1, 2, 3, 5, 8, 10, 11, 13, 15)

Universal Gates
05/20/2023
• One Type 49
– Use as many as you need (quantity), but one type only.
• Perform Basic Operations
– AND, OR, and NOT
• NAND Gate
– NOT-AND functions
– OR function can be obtained from AND by Demorgan’s
• NOR Gate
– NOT-OR functions (AND by Demorgan’s)
Digital circuits are frequently constructed with NAND or NOR gates rather
than with AND and OR gates.
NAND and NOR gates are easier to fabricate with electronic components and
are the basic gates used in all IC digital logic families.
05/20/2023
Universal Gates 50
• NAND Gate
– NOT:
– AND:
– OR:
DeMorgan’s

05/20/2023
Universal Gates 51
• NOR Gate
– NOT:
– OR:
– AND:
DeMorgan’s

05/20/2023
NAND & NOR Implementation
52
• Two-Level Implementation

05/20/2023
53
• Two-Level Implementation

05/20/2023
54
• Multilevel NAND Implementation

05/20/2023
55
• Multilevel NOR Implementation

05/20/2023
Gate Shapes 56
• AND
• OR
• NAND
• NOR

05/20/2023
Other Implementations 57
NAND and NOR logic implementations are the most
important from a practical point of view
• Some (but not all) NAND or NOR gates allow the
possibility of a wire connection between the outputs
of two gates to provide a specific logic function,
Wired Logic
• e.g.

05/20/2023
1. OR-OR
OR
With

1. OR-AND
2.
levels
Other Implementations
implementations are possible?
3. OR-NOR
NOR
58
AND, OR, NAND and NOR gates how many two
• AND-OR-Invert

2.
4. OR-NAND
OR-NAND 24
= 16

3.
5. AND-OR
6. AND-AND
AND The remaining
Those reduced to 8 a are ---
single

4.
7. AND-NOR
AND-NOR  NAND-AND
operation and
Nondegenerateare AND-NOR
called are
forms ---
8. AND-NAND
NAND equivalent
• SoP form
Degenerate or

FOR-NAND and NOR-OR are
= (AB+CD+E)’
• PoS
• OR-AND-Invert

5. NOR-OR
9. NOR-OR equivalent
 AND-OR-INVERT
10. NOR-AND
NOR  F = [(A+B)(C+D)E)]’

6.
11. NOR-NOR  OR-AND-INVERT
12. NOR-NAND
OR
13. NAND-OR
NAND

7. NAND-AND
14. NAND-AND
15. NAND-NOR
AND

8. NAND-NAND
16.
05/20/2023
Implementations Summary59
• Sum Of Products:
– AND-OR
– AND-OR-Invert = AND-NOR = NAND-AND
• Products Of Sums
– OR-AND
– OR-AND-Invert = OR-NAND = NOR--OR

05/20/2023
Exclusive-OR 60
• XOR
F=xy=xy+xy
• XNOR
F=xy=xy=xy+xy

05/20/2023
Exclusive-OR 61
• Identities
–x0=x x y XOR
–x1=x 0 0 0
–xx=0 0 1 1
1 0 1
–xx=1 1 1 0
–xy=xy=xy
• Commutative & Associative
–xy=yx
–(xy)z=x(yz)=xyz

05/20/2023
Exclusive-OR Functions 62
• Odd Function x y z XOR XNOR
0 0 0 0 1
F=xyz
0 0 1 1 0
F = ∑(1, 2, 4, 7) 0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
• Even Function 1 1 0 0 1
F=xyz 1 1 1 1 0
F = ∑(0, 3, 5, 6) yz
x 00 01 11 10
0 0 1 0 1
1 1 0 1 0

05/20/2023
Parity 63
1 1
0 0
1 0
0
0
1 1
0 0
1 0
0
0
1 1

Parity Parity
Generator Checker
05/20/2023
Parity Generator 64
• 1 Odd Parity 1
0 0
1 1
0 0
1
Odd number of ‘1’s
• Even Parity
1 1
0 0
1 1
0 0
0
Even number of ‘1’s

05/20/2023
Parity Checker 65
• 1 Odd Parity
0
1
0
Error
1
Check
• Even Parity
1
0
1
0
Error
0 Check
05/20/2023
Practice Problems 66
 3.1, 3.3, 3.5, 3.7, 3.9, 3.15, 3.16, 3.18,
3.22, 3.28
 Convert the logic diagram of the circuit
shown in Fig. 4-4 into a multiple-level
NAND circuit.

05/20/2023
Recommended Reading 67
 Acknowledgement and References:

 Chapter No. 3 Digital Design with Verilog By M. Mano and Ciletti
 These slides are obtained from Princess Sumaya University, Computer
Engineering Department Course 4241-Digital Logic Design

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EEE241

Digital Logic Design

Riaz Hussain (rhussain@comsats.edu.pk) CUI-IBD-ECE EEE241 DLD Chapter-03

Riaz Hussain (rhussain@comsats.edu.pk) CUI-IBD-ECE EEE241 DLD Chapter-03

 Chapter No. 3: Gate-Level Minimization

Riaz Hussain (rhussain@comsats.edu.pk) CUI-IBD-ECE EEE241 DLD Chapter-03

“Gate-level minimization is the design task of finding an

 Manually difficult for several inputs

“will enable you to execute a manual design of simple circuits,

Riaz Hussain (rhussain@comsats.edu.pk) CUI-IBD-ECE EEE241 DLD Chapter-03

Riaz Hussain (rhussain@comsats.edu.pk) CUI-IBD-ECE EEE241 DLD Chapter-03

Riaz Hussain (rhussain@comsats.edu.pk) CUI-IBD-ECE EEE241 DLD Chapter-03

Riaz Hussain (rhussain@comsats.edu.pk) CUI-IBD-ECE EEE241 DLD Chapter-03

Riaz Hussain (rhussain@comsats.edu.pk) CUI-IBD-ECE EEE241 DLD Chapter-03

Riaz Hussain (rhussain@comsats.edu.pk) CUI-IBD-ECE EEE241 DLD Chapter-03

Riaz Hussain (rhussain@comsats.edu.pk) CUI-IBD-ECE EEE241 DLD Chapter-03

Riaz Hussain (rhussain@comsats.edu.pk) CUI-IBD-ECE EEE241 DLD Chapter-03

Riaz Hussain (rhussain@comsats.edu.pk) CUI-IBD-ECE EEE241 DLD Chapter-03

Riaz Hussain (rhussain@comsats.edu.pk) CUI-IBD-ECE EEE241 DLD Chapter-03

Riaz Hussain (rhussain@comsats.edu.pk) CUI-IBD-ECE EEE241 DLD Chapter-03

Riaz Hussain (rhussain@comsats.edu.pk) CUI-IBD-ECE EEE241 DLD Chapter-03

Riaz Hussain (rhussain@comsats.edu.pk) CUI-IBD-ECE EEE241 DLD Chapter-03

Riaz Hussain (rhussain@comsats.edu.pk) CUI-IBD-ECE EEE241 DLD Chapter-03

A B C $ Value You can only

Riaz Hussain (rhussain@comsats.edu.pk) CUI-IBD-ECE EEE241 DLD Chapter-03

Riaz Hussain (rhussain@comsats.edu.pk) CUI-IBD-ECE EEE241 DLD Chapter-03

Finding as few Prime Implicants as Possible

Riaz Hussain (rhussain@comsats.edu.pk) CUI-IBD-ECE EEE241 DLD Chapter-03

NOTE: “Quine-McCluskey” Refers to Using a “Branch and Bound” Heuristic

2. Check Adjacent Classes for Cube Merging Building a New List

3. If Entry in New List Covers Entry in Current List – Disregard Current

4. If Current List = New List

Riaz Hussain (rhussain@comsats.edu.pk) CUI-IBD-ECE EEE241 DLD Chapter-03

Riaz Hussain (rhussain@comsats.edu.pk) CUI-IBD-ECE EEE241 DLD Chapter-03

Riaz Hussain (rhussain@comsats.edu.pk) CUI-IBD-ECE EEE241 DLD Chapter-03

Riaz Hussain (rhussain@comsats.edu.pk) CUI-IBD-ECE EEE241 DLD Chapter-03

Question: Can this be

f on = {A,B,C,D,E,F,G} = {00--, -01-, -0-0, 0-01, -101, 1-11, 11-1}

Riaz Hussain (rhussain@comsats.edu.pk) CUI-IBD-ECE EEE241 DLD Chapter-03

NOTE: Table 4.2 in book is incomplete

• C is an EPI so: f on={C, ...}

•The Row of an EPI is an

• If Column i has x’s Everywhere j Does

• If Column i is equal to Column j, eliminate Column i or if Column i

Riaz Hussain (rhussain@comsats.edu.pk) CUI-IBD-ECE EEE241 DLD Chapter-03

• No EPIs are Present

• Arbitrarily Choose F so: fon={C, F, ...}

Riaz Hussain (rhussain@comsats.edu.pk) CUI-IBD-ECE EEE241 DLD Chapter-03

Riaz Hussain (rhussain@comsats.edu.pk) CUI-IBD-ECE EEE241 DLD Chapter-03

• Secondary EPIs – A and E

Riaz Hussain (rhussain@comsats.edu.pk) CUI-IBD-ECE EEE241 DLD Chapter-03

Initial Minterm List Final Result

Riaz Hussain (rhussain@comsats.edu.pk) CUI-IBD-ECE EEE241 DLD Chapter-03

Riaz Hussain (rhussain@comsats.edu.pk) CUI-IBD-ECE EEE241 DLD Chapter-03

Riaz Hussain (rhussain@comsats.edu.pk) CUI-IBD-ECE EEE241 DLD Chapter-03

Riaz Hussain (rhussain@comsats.edu.pk) CUI-IBD-ECE EEE241 DLD Chapter-03

Riaz Hussain (rhussain@comsats.edu.pk) CUI-IBD-ECE EEE241 DLD Chapter-03

Riaz Hussain (rhussain@comsats.edu.pk) CUI-IBD-ECE EEE241 DLD Chapter-03

Riaz Hussain (rhussain@comsats.edu.pk) CUI-IBD-ECE EEE241 DLD Chapter-03